Reliable semiconductor device and method of manufacturing the same

ABSTRACT

The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor deviceconstituted of an integrated circuit having a MOS transistor formedtherein, and more particularly, to a method of forming a gate electrodefor improving reliability of a gate insulating film of the MOStransistor.

[0002] Now, we will explain steps of manufacturing the MOS transistorwhich serves as a constitutional element of an integrated circuit formedon a conventional semiconductor substrate, by taking an NMOS transistorhaving an LDD (lightly doped drain) structure, as an example. First, anelement isolating region 2 is formed on a surface region of a p-typesilicon semiconductor substrate 1 by a LOCOS method or the like. A gateinsulating film (SiO₂) 3 is formed on an element region surrounded bythe element isolating region 2. Then, boron ions are injected (channelion injection) over an entire main surface of the semiconductorsubstrate 1 to control a threshold voltage (FIG. 9A). Subsequently, apolysilicon film is deposited over the entire main surface of thesemiconductor substrate 1 and patterned to form a gate electrode 4 ofpolysilicon (PolySi) on the gate insulating film 3 in the elementregion. Thereafter, p (phosphorus) ions are injected in a low amount toform an n source/drain region 5 for mitigating a high electric field(FIG. 9B).

[0003] Next, a silicon oxide film (SiO₂) 6 is deposited on thesemiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method orthe like so as to cover the gate electrode 4 (FIG. 10A). Subsequently,the silicon oxide film 6 is anisotoropically etched to form a side wallinsulating film 7 on a side wall of the gate electrode 4. Thereafter,n-type impurity ions such as arsenic (As) ions are doped in a highamount to form an n⁺ source/drain region 8 (FIG. 10B).

[0004] As described above, in the MOS transistor, a polysilicon filmdoped with phosphorus, arsenic, or boron is generally used as the gateelectrode. The polysilicon film is deposited by an LPCVD method at areaction-chamber ambient temperature of about 600° C. The polysiliconfilm deposited under the aforementioned conditions has a film stressfilmstress of 300 MPa or more despite the presence or absence of a dopant.Such a high stress of the gate electrode is applied to a gate insulatingfilm (in this prior art, the film may be composed of a silicon oxidefilm, hereinafter simply called “gate insulating film”, for thesimplicity of explanation) whereby the high stress affects reliabilityof the gate insulating film or gate insulating film formed under thegate electrode. To explain more specifically, when the stress is appliedto the gate insulating film, the bonding between silicon and oxygenconstituting the gate insulating film is distorted. As a result, thebonding is tend to be easily broken, readily inducing dielectricbreakdown of the gate insulating film.

[0005] When intrinsic dielectric breakdown of the insulating film takesplace, the total amount Qbd of electric charge passing through theinsulating film is up to about 15 C/cm² under application of an electricfield of 12 MV/cm to the insulating film, assuming that the thickness ofthe insulating film is about 10 nm. The total charge amount Qbd is avalue on the basis of which the reliability of a transistor isdetermined. Therefore, the Qbd desirably has a large value.Particularly, in non-volatile storage device, such as EEPROM(Electrically Erasable Programmable Read Only memory) in which data iswritten into a memory cell by using a tunnel current, how many times canbe programmed is restricted by the total charge amount Qbd. Therefore,it is necessary to increase the total charge amount Qbd in order toimprove performance of the device.

BRIEF SUMMARY OF THE INVENTION

[0006] The present invention was made in view of the aforementionedcircumstances. The present invention provides a semiconductor device anda method of manufacturing the same, improved in reliability of a gateinsulating film and increased in its total charge amount Qbd bysuppressing a film stressfilm stress of a gate electrode formed of apolysilicon film, to a low value.

[0007] Since the film stressfilm stress of a gate electrode is closelyrelated with a film formation temperature, it is possible to reduce thefilm stressfilm stress lower than in the conventional case, by forming afilm at as a high temperature as 640° C. or more, preferably 650° C. ormore. With a decrease in the film stress of the gate electrode at thistime, the total charge amount Qbd of a gate insulating film underlyingthe gate electrode increases, with the result that reliability not onlyof the gate insulating film but also a semiconductor device includingthe gate insulating film is improved.

[0008] More specifically, the semiconductor device of the presentinvention comprises

[0009] a semiconductor substrate;

[0010] source/drain regions formed on the semiconductor substrate;

[0011] a gate insulating film formed between the source/drain regions onthe semiconductor substrate; and

[0012] a gate electrode formed on the gate insulating film,

[0013] in which

[0014] a film stress of the gate electrode is 200 MPa or less in termsof absolute value.

[0015] The gate electrode may be a polysilicon film and may be incontact with the gate insulating film.

[0016] A metal silicide film or a high-melting point metal film may beformed on the polysilicon film. In other words, the gate electrode maybe formed of the polysilicon film and the metal silicide film or thehigh melting point metal film. Furthermore, the high melting point metalfilm is formed on the metal silicide film, and therefore, the gateelectrode may be formed of the polysilicon film, the metal silicidefilm, and the high melting point metal film.

[0017] A MOS transistor having the source/drain regions, the gateinsulating film, and the gate electrode, may be adopted in anon-volatile semiconductor storage device such as an EEPROM. When theMOS transistor according to the invention is used in an EEPROM, theprogrammable number can be increased since a total charge amount Qbd ofelectric charge passing through the gate insulating film serving as afloating gate has a direct effect upon characteristics of a device.

[0018] According to the present invention, there is provided a method ofmanufacturing a semiconductor device, according to the present inventioncomprises the steps of:

[0019] forming source/drain regions in a semiconductor substrate;

[0020] forming a gate insulating film between the source/drain regionson the semiconductor substrate; and

[0021] forming a gate electrode including a polysilicon film on the gateinsulating film and having a film stress of 200 MPa or less;

[0022] in which

[0023] the polysilicon film is formed by depositing polysilicon on thegate insulating film by a CVD method at a temperature of 640° C. ormore. Preferably, the temperature at which a gate insulating film isformed may be 650° C. or more, in order to stably provide a gateelectrode whose film stress is 200 MPa or less.

[0024] The polysilicon film may be formed while the semiconductorsubstrate is rotated at a high speed. In this manner, it is possible toform a uniform film on a semiconductor substrate.

[0025] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0026] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0027]FIG. 1 is a schematic sectional view of a single-wafer processingLPCVD apparatus used in a first embodiment;

[0028]FIG. 2 is a cross-sectional view of a semiconductor substratehaving a MOS capacitor according to the present invention;

[0029]FIG. 3 is a characteristic graph showing the relationship betweendeposition temperature of a polysilicon film and film stress;

[0030]FIGS. 4A and 4B show that a semiconductor substrate is bent by acompression stress or tensile stress generated in a gate electrode(polysilicon film);

[0031]FIGS. 5A and 5B are conceptual diagram for explaining how a bentamount is calculated, FIG. 5A relates to the situation prior to theformation of a polysilicon film on the silicon substrate, and FIG. 5Brelates to the situation after the formation of a polysilicon film onthe silicon substrate.

[0032]FIG. 6 is a characteristic graph showing the relationship betweenthe film stress of the polysilicon film and the total charge amount of agate insulating film;

[0033]FIG. 7 is a schematic sectional view of a single-wafer processingLPCVD apparatus used in a second embodiment;

[0034]FIG. 8 is a cross sectional view of EEPROM according to a thirdembodiment;

[0035]FIGS. 9A and 9B are cross sectional views showing manufacturingsteps of a semiconductor substrate having a conventional MOS transistor;and

[0036]FIGS. 10A and 10B are cross sectional views showing themanufacturing steps of a semiconductor substrate having a conventionalMOS transistor.

DETAILED DESCRIPTION OF THE INVENTION

[0037] Now, embodiments of the present invention will be explained withreference to the accompanying drawings.

[0038] First, referring to FIGS. 1 to 6, a first embodiment will beexplained.

[0039]FIG. 1 is a schematic sectional view of a single-wafer processingLPCVD (Low pressure CVD) apparatus.

[0040]FIG. 2 is a cross sectional view of a MOS capacitor formed on asemiconductor substrate. FIG. 3 is a characteristic graph showingdependency of the film stress (MPa) of the polysilicon film on thesemiconductor substrate upon deposition temperature. FIGS. 4A to 5B areconceptual diagram explaining the way of measuring a film stress. FIG. 6is a characteristics graph showing a total charge amount Qbd (C/cm²) ofthe gate insulating film.

[0041] As shown in FIG. 1, the LPCVD apparatus has a reaction chamber 13(hereinafter, referred to as “film formation chamber”). Thefilm-formation chamber 13 is equipped with a susceptor 15 on which asemiconductor wafer 16 is mounted. The inner space of the film formationchamber 13 is heated by a plurality of infrared lamps 14 arranged aroundthe chamber in close proximity thereto, during film formation time. Areactive gas is supplied from a pipe 10 to the inner space of the filmformation chamber 13 while being controlled by a mass-flow controller 11and a valve 12. After completion of a reaction, an exhaust gas isdischarged by a pump 112 through a pipe 111. The pump 112 is controlledby a valve 18 and a conductance valve 19 while the pressure is monitoredby a pressure gage 17 attached to the pipe 111.

[0042] As shown in FIG. 2, an thermal oxidation film serving as a gateinsulating film 122 and formed on a silicon semiconductor substrate 121is oxidized with O₂, H₂O, or HCl gas at a temperature of 800° C. torender the thickness at 8 nm. Thereafter, the semiconductor substrate121 (semiconductor wafer 16) is placed in the film-formation chamber 13of the LPCVD apparatus shown in FIG. 1. Then, a polysilicon film 123 isformed on the semiconductor wafer 16 in a thickness of about 200 nm at afilm-formation temperature of 680° C. and a pressure of 5 Torr whileSiH₄ gas is supplied at a flow rate of 1 SLM and ASH₃ gas at a flow rateof 1 sccm. At this time, the concentration of As in the polysilicon film123 is about 1×1020 atoms/cm³. Thereafter, the polysilicon film 123 isannealed for 30 minutes at 900° C. under an N₂ atmosphere in order toactivate a dopant. Thereafter, a photoresist (not shown) is coated ontothe polysilicon film 123 and photolithographically patterned. Thepolysilicon film 123 is further subjected to dry etching in accordancewith anisotropic etching such as RIE (Reactive Ion Etching) to form thegate electrode 123 a. Finally, a capacitor of a layered structure: agate electrode—gate insulating film—a semiconductor substrate, wasformed. Then, electric characteristics of the gate insulating film wereexamined by using the capacitor. In this embodiment, the gate electrode123 a is formed of polysilicon film 123, but the material of the gateelectrode according to the present invention is never limited to apolysilicon, as being explained later. In the case that a deviceaccording to the present invention is actually fabricated, source/drainregions 124 are formed in the semiconductor substrate 121. However, inthe case of examining the electric characteristics of gate insulatingfilm, the formation of source/drain regions 124 is omitted since theyare unnecessary in the above examination.

[0043]FIG. 3 shows the relation between a deposit temperature of apolysilicon film (gate electrode) and a film stress. In FIG. 3, thelongitudinal axis indicates a film stress (MPa) of the polysilicon filmon the semiconductor substrate, and the lateral axis indicates the filmformation temperature (° C.) of the polysilicon film. The polysiliconfilms were formed by deposited on the substrate in the same manner underthe same conditions as in the aforementioned steps for manufacturing acapacitor, except the film formation temperature, that is, by varyingthe film formation temperature, and then annealing the polysilicon film,whereby obtaining various semiconductor wafers having capacitors ofvarious electric characteristics. Thereafter, the stress of thepolysilicon film alone was checked on the basis of warpage of thesemiconductor wafer.

[0044] The stress of the polysilicon film itself was measured asfollows.

[0045] Generally, compressive stress or tensile stress is generated inthe polysilicon film, depending upon a deposition temperature of thepolysilicon film. When the compressive stress is generated, “upwardwarpage” bent is produced, as shown in FIG. 4A. On the other hand, whenthe tensile stress is generated, “downward warpage” bent is produced, asshown in FIG. 4B. Hereinafter, the “upward warpage” bent will beexpressed by a positive value, whereas the “downward warpage” bent by anegative value.

[0046]FIGS. 5A and 5B are conceptual views showing how to obtain awarpage amount, arithmetically. FIG. 5A shows a state before thepolysilicon film is deposited on a substrate. FIG. 5B shows a stateafter the polysilicon film is deposited on the substrate. In thefigures, reference symbol ts denotes a thickness of a substrate, tr is athickness of the deposited film (polysilicon film), D is a diameter ofthe portion at which warpage is measured (corresponding to the warpage),and X is a warpage amount (μm).

[0047] The film stress a may be arithmetically obtained in accordancewith a general equation for stress:$\sigma = {\frac{E_{s}}{6( {1 - \gamma_{s}} )} \cdot \frac{( t_{s} )^{2}}{t_{r}} \cdot \frac{1}{r}}$

[0048] where σ is a film stress, Es is a Young's modulus of a substrate(semiconductor wafer), and γ_(s) is a Poisson's ratio of the substrate.

[0049] Herein, from the following Equation I: $\begin{matrix}\begin{matrix}{r = {{\frac{X^{2} + ( {D/2} )^{2}}{2X} \approx \frac{( {D/2} )^{2}}{2X}} = \frac{D^{2}}{8X}}} \\{\because{Xr}}\end{matrix} & (I)\end{matrix}$

[0050] Equation II is deduced. $\begin{matrix}{\sigma = {{\frac{E_{s}}{6( {1 - \gamma_{s}} )} \cdot \frac{( t_{s} )^{2}}{t_{r}} \cdot \frac{1}{r}} \approx {\frac{E_{s}}{6( {1 - \gamma_{s}} )} \cdot \frac{( t_{s} )^{2}}{t_{r}} \cdot \frac{8X}{D^{2}}}}} & ({II})\end{matrix}$

[0051] Accordingly, stress a is obtained on the basis of the warpageamount X. As mentioned before, since a “upward warpage” is defined as apositive value, and a “downward warpage” a negative value, a film stressin the case of “upward warpage” has a positive value, while a filmstress in the case of a “downward warpage” has a negative value.

[0052] The film stress of the polysilicon film alone is defined as thedifference in warpage amount before and after the polysilicon film isdeposited, as being illustrated in FIGS. 5A and 5B. The warpage amountis measured by using Flexsus FLX-2418 (manufactured by KLA TencorCorporation), as a measuring device.

[0053] Referring again to FIG. 3, it has been found that the film stressis as small as 50MPa (absolute value) or less at a depositiontemperature of 700° C. or more. As the film formation temperaturedecreases from 700° C., a compressive stress is expressed, while atensile stress reaches as large as −300 MPa at near 620° C. On the otherhand, the stress immediately after the polysilicon film is formed, is100 MPa or less. This value does not so significantly differ from thatobtained after the annealing.

[0054]FIG. 6 shows the results of a total charge amount Qbd of the gateinsulating film measured under an electric field of 12 MV/cm, in the MOScapacitor thus formed on the semiconductor substrate. Note that thetotal charge amount Qbd is defined as the total amount of electriccharge passing through the capacitor per unit area when a plurality ofcapacitors formed in the same plane of the semiconductor wafer aremeasured and a failure rate thereof reaches 50%.

[0055] In the case where the film stress is smaller than −300 MPa, thetotal amount of the electric charge Qbd is about 15 C/cm². However, inthe case where the film stress ranges from −200 MPa to about +30MPa, thetotal charge amount Qbd is as large as 25 C/cm² or more. This means thatthe total charge amount of the gate insulating film 122 is 25 C/cm² ormore when the polysilicon film forming gate electrode 123 a is formed ata film formation temperature of 640° C. or more, preferably 650° C. ormore. In addition, in a preferable embodiment, the atmosphere pressurein depositing a polysilicon film serving as a gate electrode may be in arange of 20 to 200 Torr.

[0056] In this embodiment, a single-wafer processing LPCVD apparatus isused. In the present invention, however, a batch processing LPCVDapparatus usually employed in manufacturing a semiconductor device, maybe used.

[0057] By using the batch processing LPCVD apparatus, the polysiliconfilm serving as the gate electrode was formed, at a temperature from500° C. to 630° C. and a pressure from 0.3 Torr to 1 Torr while SiH₄ gasis supplied at a flow rate from 200 sccm to 1000 sccm. As a result, thepolysilicon film formed at a temperature of 580° C. or more wascrystallized. At this time, the film stress was −300 MPa or less (300MPa or less in terms of absolute value).

[0058] The results for the MOS capacitor manufactured by the batchprocessing LPCVD apparatus were the same as those of the MOS capacitormanufactured by the single-wafer processing LPCVD apparatus. That is,the total charge amount Qbd causing dielectric breakdown of the gateinsulating film was about 15 C/cm². Furthermore, the silicon filmdeposited at a film formation temperature of 580° C. or less is in anamorphous state and has a compressive film stress of about −300 MPa. Theamorphous film is crystallized into a polysilicon film in the annealingstep performed later. The film stress of the polysilicon film greatlyincreases to a tensile stress of about 300 MPa in absolute value. Whensuch a polysilicon film is used, the total charge amount of the gateinsulating film comes to about 15/cm². The MOS capacitor manufactured bythe batch processing LPCVD apparatus satisfies the same relationshipbetween the total charge amount Qbd of the gate insulating film and thefilm stress of the gate electrode shown in FIGS. 3 and 6.

[0059] The same results as in the aforementioned embodiment are given inthe case where MOS capacitor having a polysilicon film doped withphosphorus (P) or boron (B) is used in place of the film doped witharsenic (As). Furthermore, even if the concentration of the dopant isvaried, the same results are obtained. Thus, it has been found that thefilm stress of a gate electrode is determined mainly by its filmformation temperature, regardless of dopant materials or dopantconcentration.

[0060] The gate insulating film of 8 nm thick is used in thisembodiment. When the film thickness of the oxide film is changed, thetotal charge amount of the gate insulating film varies, accordingly.When the film thickness of the gate insulating film decreases, the totalcharge amount Qbd reduces, whereas when the film thickness increases,the total charge amount Qbd increases. However, the relationship betweenthe film stress and the total charge amount of the gate insulating filmis unchanged. That is, when the film stress of the gate electrodeincreases, the total charge amount of the gate insulating filmdecreases. To be more specific, when the film stress is 200 MPa or less,the total charge amount Qbd is about twice as large as that obtained atthe film stress of 300 MPa.

[0061] In the case where the gate electrode is formed of anothersubstance such as a metal including tungsten (W), the effect of the filmstress upon the total charge amount Qbd of the gate insulating film issimilar and thus, the same phenomenon is observed. Hence, when the metalelectrode is used, it is effective to set the film stress of the gateelectrode at 200 MPa or less in terms of absolute value, in order toimprove the total charge amount Qbd of the gate insulating film, inother word, to improve reliability thereof.

[0062] Referring to FIG. 7, a second embodiment will be explained.

[0063] In the first embodiment, a single-wafer processing LPCVDapparatus is used. When the single-wafer processing LPCVD apparatus isheated at high temperatures, the formed film is sometimes degraded inuniformity in thickness. To maintain the uniformity of film thickness,the semiconductor wafer is rotated in the apparatus.

[0064]FIG. 7 is a schematic sectional view of the single-waferprocessing LPCVD apparatus. As shown in the figure, the LPCVD apparatushas a reaction chamber (film formation chamber) 21. In the filmformation chamber 21, a wafer holder 22 is provided for mounting asemiconductor wafer 24 thereon. The wafer holder 22 is designed so as torotate at a predetermined rotation number to rotate the semiconductorwafer 24. The film formation chamber 21 has a heater 23 therein forheating an inner space during film formation time. A reactive gas issupplied to the inner space of the film formation chamber 21 from a pipe20 while being controlled by a mass-flow controller 27 and a valve 26.After completion of a reaction, an exhaust gas is discharged through apipe 211 by a pump 210. The pump 210 is controlled by a valve 28 and aconductance valve 29.

[0065] A gas flow 25 of the reactive gas supplied through the pipe 20enters from an upper portion of the film formation chamber 21, passesthrough slits and is supplied uniformly over a surface of thesemiconductor wafer 24 in rotation. After completion of a reaction, thegas flow 25 is discharged from the pipe 211.

[0066] A semiconductor wafer was placed in the single-wafer processingLPCVD apparatus thus constructed and a reactive gas flow was supplieduniformly over the surface of the semiconductor wafer while thesemiconductor wafer was rotated at a high speed. In this manner, apolysilicon film was formed on a semiconductor wafer. When thepolysilicon film was formed by supplying SiH₄ at a flow rate of 1 SLM,ASH₃ at a flow rate of 3 sccm under a pressure of 50 Torr, and N₂ at aflow rate of 30 SLM, while the semiconductor wafer was rotated at arotation number of 3000 rpm, the resultant polysilicon film wasexcellent in uniformity (±3% or less) in thickness within thesemiconductor wafer surface plane at the film formation temperatureranging from 600° C. to 900° C. In this case, the film stress of thepolysilicon film satisfied the same relationship between the filmformation temperature and the film stress shown in FIG. 3. Then, MOScapacitors were formed on a semiconductor substrate and a total chargeamount Qbd determining dielectric breakdown of the gate insulating filmsof the capacitors was examined and measured. The results are the same asshown in FIG. 6. That is, according to the second embodiment, it ispossible to provide a semiconductor device having a highly liable gateinsulating film, with keeping a very preferable uniformity in filmthickness.

[0067] Now, referring to FIG. 8, a third embodiment will be explained.

[0068]FIG. 8 is a cross sectional view of an EEPROM memory cellaccording to the third embodiment of the invention. The EEPROM is anon-volatile electrically erasable and programmable memory, and mostlyused in a new fields including a logic array capable of programming datamemory and logic in a logic circuit, e.g., a micro computer, datamemories, and program memories of IC cards.

[0069] As the semiconductor substrate, for example, a p-typesemiconductor substrate 31 is used. The surface of the semiconductorsubstrate 31 is oxidized with O₂, H₂O, or HCl gas at a temperature of800° C. to form a thermal oxide film 34 of 8 nm thick serving as a gateinsulating film.

[0070] Thereafter, the semiconductor substrate 31 is placed as asemiconductor wafer in the film formation chamber of the LPCVD apparatusshown in FIG. 1. A polysilicon film 35 constituting a floating gate isformed on the semiconductor wafer of about 200 nm thick at a filmformation temperature of 680° C. while SiH₄ gas is supplied at a flowrate of 1 SLM and AsH₃ gas at 1 sccm under a pressure of 5 Torr. Thefilm stress of polysilicon film 35 can be suppressed less than about 200MPa in its absolute value by forming polysilicon film in the same manneras above the first embodiment or the second embodiment. As a result thepolysilicon film 35 constituting a floating gate can have a total chargeamount Qbd as twice large as a conventional one, so that a semiconductordevice having a highly liable floating gate can be provided.

[0071] At this time, arsenic (As) is introduced into the polysiliconfilm 35 in an amount of about 1×10²⁰ atoms/cm³. Thereafter, thepolysilicon film 35 is annealed at 900° C. for 30 minutes under a N₂atmosphere in order to activate a dopant.

[0072] Subsequently, a photoresist (not shown) is coated onto thepolysilicon film 35 and photolithographically patterned. The resultantpolysilicon film 35 is etched by a RIE method to form a floating gate 35of polysilicon. Then, an interlayer insulating film (SiO₂) film 36 isformed on the semiconductor wafer by a CVD method so as to cover thefloating gate 35. Subsequently, a polysilicon film 37 is formed on thesemiconductor wafer of about 200 nm thick, for example, in the LPCVDapparatus shown in FIG. 1, in the same conditions as in the formationtime of the floating gate 35. At this time, Arsenic (AS) is introducedinto the polysilicon film 37 in an amount of about 1×10²⁰ atoms/cm³.Thereafter, the polysilicon film 37 is annealed at 900° C. under a N₂atmosphere in order to activate a dopant. Thereafter, a photoresist (notshown) is coated onto the polysilicon film 37 and photolithographicallypatterned. The polysilicon film 37 is etched by RIE to form a controlgate 37 of polysilicon.

[0073] Note that the single-wafer processing LPCVD apparatus shown inFIG. 1 is used in this case, however, the polysilicon film forming thegate electrode may be formed in the single-wafer processing LPCVDapparatus shown in FIG. 7.

[0074] Then, n-type impurity ions such as boron are doped in thesemiconductor substrate 31 by using the control gate 37 as a mask andthermally diffused to form an n⁺ source region 32 and an n⁺ drain region33. Then, an insulating film (SiO₂) 38 is deposited by the CVD method onthe semiconductor substrate 31 so as to cover the control gate 37. Thesurface of the insulating film 38 is planarized by a CMP (ChemicalMechanical Polishing) method. Then, a photoresist (not shown) is coatedonto the insulating film 38 and photolithographically pattered. Theresultant insulating film 38 is etched by RIE etc. to form a contacthole 38 through which the drain region 33 is exposed. Subsequently, analuminium film 310 is deposited by a sputtering method on the insulatingfilm 38 and within the contact hole 39, and photolithographicallypatterned to form a metal wiring 310.

[0075] As for the device such as EEPROM for writing data into a memorycell by using a tunnel current, the Qbd value is significant since itdetermines how many times the device can be programmed. Therefore, it isnecessary to increase the total charge amount Qbd in order to improvethe performance of the device. In the EEPROM in which the total amountQbd of the electric charge passing through the gate insulating filmdirectly influences upon characteristics of a device, the number oftimes the device can be programmed or rewritten is greatly improved bythe present invention. Since the film stress of the gate electrodeaccording to the present invention is suppressed to 200 MPa or less interms of absolute value, the total charge amount Qbd of the gateinsulating film increases nearly double. As a result, the life spans oftransistors and LSI products having the MOS structure increase double,increasing reliability of the device. This feature is particularlyuseful in EEPROM in which the total charge amount Qbd directlyinfluences upon characteristics of a device, since the number of timesthe device can be programmed or rewritten increases approximatelydouble.

[0076] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; source/drain regions formed on thesemiconductor substrate; a gate insulating film formed between thesource/drain regions on the semiconductor substrate; and a gateelectrode formed on the gate insulating film, wherein a film stress ofthe gate electrode is 200 MPa or less in terms of absolute value.
 2. Thesemiconductor device according to claim 1, wherein the gate electrode isin contact with the gate insulating film.
 3. The semiconductor deviceaccording to claim 1, wherein said gate electrode is formed of apolysilicon film.
 4. The semiconductor device according to claim 1,wherein the gate electrode comprises at least one of a metal silicidefilm and a high-melting point metal film.
 5. The semiconductor deviceaccording to claim 4, wherein the high melting point metal film isformed on the metal silicide film
 6. A non-volatile semiconductor devicecomprising: a semiconductor substrate; source/drain regions formed onthe semiconductor substrate; a gate insulating film formed between thesource/drain regions on the semiconductor substrate; and a floating gateformed on the gate insulating film, wherein a film stress of thefloating gate is 200 MPa or less in terms of absolute value.
 7. A methodof manufacturing a semiconductor device, comprising the steps of:forming source/drain regions in a semiconductor substrate; forming agate insulating film between the source/drain regions of thesemiconductor substrate; and forming a gate electrode formed of apolysilicon film on the gate insulating film; wherein a film stress ofthe gate electrode is 200 MPa or less in terms of absolute value.
 8. Themethod according to claim 7, wherein the gate electrode comprises apolysilicon film which is formed by depositing the gate insulating filmby a CVD method at an atmosphere temperature of 640° C. or more.
 9. Themethod according to claim 8, wherein the atmosphere temperature is 650°C. or more.
 10. The method according to claim 8, wherein the step offorming the gate electrode includes a step of forming a polysilicon filmwhile rotating the semiconductor substrate at a high speed.
 11. Themethod according to claim 10, wherein the rotation speed is 3000 rpm ormore in the step of forming a polysilicon film while rotating thesemiconductor substrate.
 12. The method according to claim 7, whereinthe gate electrode is a floating gate.